Date: November 28, 2025
Time: 10:00-11:30
Place: 京都大学 総合研究9号館 N1講義室 (北館 1F)
(以下の地図の#63の建物)
https://www.kyoto-u.ac.jp/ja/access/campus/yoshida/map6r-y

プログラム
10:00-11:00
- 講演タイトル
Physical Design for Heterogeneous Integration: Challenges and Opportunities
- 講演者
Prof. Yao-Wen Chang
Dept. of Electrical Engineering, National Taiwan University
- 概要
To achieve the power, performance, and area (PPA) target in modern
semiconductor design, the trend to go for More-than-Moore
heterogeneous integration by packing various components/dies into a
package becomes more obvious as the economic advantages of More-Moore
scaling for on-chip integration are getting smaller and smaller.
Heterogeneous integration refers to integrating separately
manufactured components into a higher-level assembly (such as advanced
packaging and even multiple packages in a PCB) that provides enhanced
functionality and improved operating characteristics. Unlike the
on-chip designs with relatively regular components and wirings, the
physical design problem for heterogeneous integration often needs to
handle arbitrary component/board shapes, diverse metal line widths,
and different spacing requirements between components, wire metal, and
pads, with multiple cross-physics domain considerations such as
system-level, physical, electrical, mechanical, thermal, and optical
effects, which are not well addressed in the traditional chip design
flow. In this talk, we first introduce popular heterogeneous
integration technologies and options, their layout modeling and
induced physical design problems, survey key published techniques, and
provide future research directions for modern physical design problems
for heterogeneous integration.

11:00-11:30
- 講演タイトル
- 講演者
Prof. Jai-Ming Lin
Dept. of Electrical Engineering, National Cheng Kung University
- 概要
Wire bonding remains one of the most widely adopted signal transmission
techniques in system-in-package (SiP) and wire-bonding package designs,
serving as a key interconnection method between die I/O pads and substrate
bonding fingers. Although the placement of bonding fingers has a critical
impact on both cost and performance, current industrial workflows still
rely largely on manual or semi-automated processes. The irregular
geometries and arbitrary orientations of bonding fingers, together with
stringent design constraints—such as avoiding wire crossings—make this
placement problem highly complex and unsuitable for standard System-
on-Chip (SoC) placement algorithms.
In this work, we present the first fully automated finger placement tool
developed for ASE Corp. The proposed framework consists of two main
stages: a global distribution stage and a legalization stage. To achieve
accurate wirelength estimation and efficient space utilization, we introduce
a double-square model that captures both the geometry and orientation of
bonding fingers. Based on this model, we formulate an analytical global
placement method that minimizes wirelength while simultaneously
determining the positions and orientations of the fingers. To support this
optimization, minor design rule violations and small overlaps are
temporarily permitted. We then develop a legalization algorithm inspired
by Abacus to enforce spacing and design rules while preserving the
relative placements obtained from the global stage. Experimental results
demonstrate that our approach can produce legal and compact multi-row
placements with significantly reduced wirelength compared to
conventional rectangular models, providing a practical and fully automated
solution for next-generation wire-bonding design.

- 講演者略歴
Prof. Yao-Wen Chang
Yao-Wen Chang received a B.S. degree from National Taiwan University
(NTU), Taiwan, in 1988 and M.S. and Ph.D. degrees from the University
of Texas at Austin in 1993 and 1996, respectively, all in computer
science.
Dr. Chang is a Fellow of the ACM, the CIEE, and the IEEE. He is a Past
President of the IEEE Council on Electronic Design Automation (CEDA).
He is currently a Distinguished Professor of the Dept. of Electrical
Engineering at NTU after serving as the Dean of the College of
Electrical Engineering and Computer Science 2018-2024. He was Deputy
Vice President for Academic Affairs of NTU 2016-2018. Dr. Chang was a
visiting professor at Waseda University in Japan 2005--2010 and a
visiting scholar at the Massachusetts Institute of Technology (MIT) in
2014.
His current research interests lie in electronic design automation. He
has co-authored about 400 ACM/IEEE conference/journal papers in these
areas (101 papers in DAC [#1 worldwide], 81 papers in ICCAD [#2
worldwide], and 88 papers in TCAD [#3 worldwide]), including highly
cited works on floorplanning, placement, routing, design for
manufacturability, and FPGA.
He has received 13 Best Paper Awards (including ICCAD’25, DAC’17,
ICCD’10, ICCD’95). He has received two NTU distinguished teaching
awards, nine NTU excellent teaching awards.

Prof. Jai-Ming Lin
Jai-Ming Lin (Member, IEEE) received the B.S., M.S., and Ph.D. degrees
from National Chiao Tung University, Hsinchu, Taiwan, in 1996, 1998,
and 2002, respectively, all in computer science.
From 2002 to 2007, he was an Assistant Project Leader with the CAD
Team, Realtek Corporation, Science Park, Hsinchu. He is a Professor
with the Department of Electrical Engineering, National Cheng Kung
University, Tainan, Taiwan. His research focuses on physical design
especially in the topics such as floorplanning, placement, and
powerplanning for 2D, 2.5D, and 3D-ICs.

事前参加申し込み: 不要
参加費: 無料
共催 IEEE CASS Kansai Chapter, CEDA All Japan Joint Chapter

問い合わせ先
橋本昌宜 (京都大学) hashimoto@i.kyoto-u.ac.jp