IEEE CASS Kansai Chapter Seminar

Date: January 17, 2024
Time: 14:00-15:00
Place: 京都大学 総合研究9号館 N2講義室 (北館 2F)
(以下の地図の#63の建物)
https://www.kyoto-u.ac.jp/ja/access/campus/yoshida/map6r-y

- 講演タイトル
Introduction to Analysis and Debugging of Transient Faults
- 講演者
Prof. Jing-Jia Liou
Dept. Electrical Engr., National Tsing Hua Univ, Taiwan
- 概要
Transient fault is an error model that flips a register or memory bit
at certain cycles of a digital circuit, e.g, a processor core. The
model is commonly applied in evaluating the reliability of a digital
system including both software and hardware. For example, we may
inject sampled transient faults and run a software to observe the
hardware faulty behavior, so error outputs can be analyzed and
mitigated. On the other hand, when a system captures and shows error
symptom during validation, a debugging process will often start with
tracing the root cause to a certain transient fault and then follow up
with failure analysis. For both above applications, we face the issue
that the number of transient faults is simply too large for a full
comprehensive analysis. In this talk, we will introduce and discuss
methods on how to analyze and reduce the number of transient faults.
In our experiments with two RISC-V cores, only under 1-3% of faults
remains necessary for processing, which can drastically improve our
reliability analysis for a digital system.
- 講演者略歴
Jing-Jia Liou graduated from UC Santa Barbara. He is currently the
Chairman and Professor with the National Tsing Hua University,
Hsinchu, Taiwan. He is also the director of NTHU-MediaTek research
center, and director of Design department of NTHU Collage of
Semiconductor Research. He also serves as a research consultant at
Industrial Technology Research Institute (ITRI). His research
interests include electronic system level modeling, design and test,
design for reliability and safety, and machine-learning techniques for
test data analysis.
Prof. Liou was a recipient of best paper awards from the IEEE
Conference of Design, Automation, and Test in Europe (DATE 2004) and
the Asian Test Symposium (ATS 2009). He also received MXIC Golden
Silicon advisor award at 2010, and National Invention and Creation
Award in 2019. He served on several technical committees, including
DAC, HPCA, ASPDAC, ATS, ICCD, VLSI-SOC and ITC-Asia.

事前参加申し込み: 不要
参加費: 無料
主催 IEEE CAS 関西チャプター

問い合わせ先
橋本昌宜 (京都大学) hashimoto@i.kyoto-u.ac.jp