IEEE CASS Kansai Chapter Seminar

Date: September 22, 2023
Place: N2 lecture room, 2F, Research Building #9
   Yoshida campus, Kyoto University
(Building #63 in the map below)
https://www.kyoto-u.ac.jp/ja/access/campus/yoshida/map6r-y

Agenda:
14:00 Talk by Prof. Youngsoo Shin, KAIST (including 5-min Q&A)
- Title
EDA with ML, Rule-Based, or Both?
- Abstract
Machine learning (ML) has been effectively applied to many
applications these days mainly because huge amount of data is
available through internet. This is not the case in semiconductor
industry, where data is not shared between companies or even inside a
single organization. This talk tries to compare ML and rule-based
methods when data volume is high and low. The expectation is that ML
is more efficient with high data volume and rule-based is less
sensitive to the amount of data and so can be a better choice in low
data volume. In addition, combining both methods in a way that rules
are revised with some guidance from ML model is investigated so that
rule-based method can be a good option in low data volume.
- Bio
Youngsoo Shin is a Professor, a holder of the ICT Endowed Chair, in
the School of EE at KAIST. Prior to joining KAIST in 2004, he was a
Research Staff Member at IBM T.J. Watson Research Center, NY.
Currently, he is also a CEO of Baum, which specializes high-level
power modeling and fast power analysis. He is Outside Director of LX
Semicon since 2018. He was Associate Editor of IEEE TCAD, IEEE D&T,
and ACM TODAES, and was involved in a number of conferences including
DAC, ICCAD, ASP-DAC, DATE, and ISLPED as organizing/steering/program
committee member. He is a Fellow of the IEEE.

14:20 Talk by Prof. Woojoo Lee,  Chung-Ang University (including 10-min Q&A)
- Title:
RISC-V eXpress: Streamlining Swift and Simple RISC-V Processor Development
Abstract:
With the advantages of the BSD (Berkeley Software Distribution)
license, compact chip area, and low power consumption, RISC-V cores
are anticipated to lead the edge device market. They are garnering
explosive interest from both academia and industry. However, the
reality is that the barriers to designing a new processor using RISC-V
cores have appeared considerably high. In this talk, I introduce the
RISC-V eXpress (RVX), a groundbreaking tool developed to simplify and
expedite the design of RISC-V processors using open RISC-V cores. Not
only does RVX offer a range of RISC-V cores, but it also presents a
comprehensive list of essential IPs for processors. Developers merely
need to select the desired IPs, and RVX automatically assembles a
processor with those IPs. In essence, RVX provides the complete RTL
code of the processor and the bitstream necessary for FPGA prototyping
to the developer. Throughout this presentation, I will showcase
various RISC-V processor examples crafted using RVX.
Bio:
Woojoo Lee received the B.S. degree in electrical engineering from
Seoul National University, Seoul, South Korea, in 2007, and the M.S.
and Ph.D. degrees in electrical engineering from the University of
Southern California, Los Angeles, CA, USA, in 2010 and 2015,
respectively. He was a Senior Researcher with the Electronics and
Telecommunications Research Institute, Daejeon, Korea, from 2015 to
2016, and an Assistant Professor with the Department of Electrical
Engineering, Myongji University, Seoul, from 2017 to 2018. He has been
serving as an Associate Professor in the School of Electrical and
Electronics Engineering at Chung-Ang University, Seoul, Korea, since
2019. His research interests include ultra-low power VLSI designs,
System-on-Chip designs, spiking neural network designs, and
system-level power and thermal management.

15:10 closing

事前参加申し込み: 不要
参加費: 無料
主催 IEEE CAS 関西チャプター

問い合わせ先
橋本昌宜 (京都大学) hashimoto@i.kyoto-u.ac.jp