IEEE
EDS Japan Chapter 会員各位
IEEE
EDS Kansai Chapter 会員各位
IEEE
SSCS Japan Chapter 会員各位
IEEE
SSCS Kansai Chapter 会員各位
IEEE Electron Devices Society Japan Chapter
Chair 小柳 光正
Vice Chair 木村 紳一郎
【ナノシリコン国際ワークショップ】
「G-COE
PICE International Symposium on Silicon Nano Devices in 2030:
Prospects by World’s Leading Scientists」
IEEE
EDS Japan Chapterが共催しております【ナノシリコン国際ワークショップ】
「G-COE
PICE International Symposium on Silicon Nano Devices in 2030:
Prospects by World’s Leading Scientists」を開催いたします。奮って
ご参加いただきたく、ご案内申し上げます。
【ナノシリコン国際ワークショップ】
「G-COE
PICE International Symposium on Silicon Nano Devices in 2030:
Prospects
by World’s Leading Scientists」
【開催日程】10月13日（火）、14日（水）
【開催場所】東京工業大学蔵前会館 東工大蔵前会館 くらまえホール
（東急目黒線・大井町線、大岡山駅前）
【連絡先】東京工業大学 G-COE拠点室
<venus@gcoe-pice.titech.ac.jp>
TEL 03-5734-2556
【参加費】無料
事前登録必要； 10月10日締め切り
下記サイトでお申し込み頂けましたら幸いでございます。
http://www.gcoe-pice.titech.ac.jp/symposium-oct09/index.html
どうぞよろしくお願い申し上げます。
主催 東京工業大学
共催 IEEE
EDS Japan Chapter
技術共催：IEEE
EDS、応物シリテク分科会
後援：NEDO,
JST
【主旨】
テーマ： シリコンナノデバイス2030年の世界：世界の英知を集結して討論する
- 20年後のデバイスの次元は？
3次元？2次元？1次元？0次元？それとも異次元？
- 微細化限界到達後の電子デバイスの世界は？
Si-CMOSが依然として主流の地位を保てるか？
そうでなければ本命はどのデバイスか？どの材料か？また本命となる条件は？
-ポストCMOSデバイスが切り拓く新たなアプリとは？
トランジスタ寸法の微細化は５０年間に渡って着実に進展し、集積回路の性能がムー
アの法則に従って指数関数的に向上した結果、今日の高度情報通信社会を築いてきま
した。しかし、トランジスタの寸法がナノメートルのスケールになった今、このよう
な微細化に基づく性能向上限界の議論が盛んになってきています。MOSFETの構造は、
従来の平面型ゲート電極構造から、立体的なゲート電極構造への転換が始まり、その
究極的な形状として、理想的なゲート電界分布が得られる１次元ナノワイヤ構造の研
究が盛んに行われています。
一方、０次元量子ドット構造も、クーロンブロッケード、バリスティック伝導、高
効率発光、電子放出などの量子効果現象が観測され、新しい応用展開が期待できま
す。
さらに、カーボンなどの新しい材料や、従来の電荷を担体とするエレクトロニクスを
超えるデバイス、例えばスピンデバイスなどの研究も盛んです。
この国際シンポジウムでは、半導体デバイスの教科書で有名なS.M.Sze博士をはじ
め、
シリコンナノデバイス研究の世界の第１人者を招聘して、今後20年後のシリコンデバ
イスの将来は何かを探ることを目的としています。
【プログラム】
Tuesday,
13 October
Opening
Session
10:00 K. Iga, (President, Tokyo Tech.) Welcome Remark
10:10 S. Kimura (Vice Chair, IEEE EDS Japan
Chapter/ Hitachi Ltd) “
Greetings
from IEEE EDS”
10:15 T. Sugano (Professor Emeritus, Univ.
Tokyo) “Silicon Nano-Devices;
Physics and Usefulness”
10:35 S. M. Sze (Bell Lab, U.S.A. & National
Chao Tung Univ., Taiwan) Special Lecture
“My years at Bell Laboratories (1963-1989) ”
11:35 Lunch Break
Session
1
12:30 H. Iwai (Tokyo Tech.) “Miniaturization and future prospects of
Si devices”
13:00 K. Shiraishi (Tsukuba Univ.) “Physics for Si nanowire FET and its
fabrication”
13:30 A. Oshiyama (Univ. Tokyo) “Large-Scale Density-Functional
Calculations for Atomic and Electronic Structures of Si Nanowires”
14:00 N. Sano (Tsukuba Univ.) “Simulation of Electron Transport in Si
Nano Devices”
14:30 K. Natori (Tokyo Tech.) “A Compact Modeling of Quasi-Ballistic
Si Nanowire MOSFET”
15:00-15:30 Break and Poster session
Session
2
15:30 G. Baccarani (Univ. Bologna)
“Effective
Mobility and Backscattering Coefficients in Short Gate-Length Nanowire FETs”
16:00 Dim-Lee Kwong (IME, Singapore)
“Prospects
of Silicon Nanoelectronics with Vertical Nanostructures, Their Challenges and
Solutions”
16:30 S. Deleonibus (LETI, France)
“NanoCMOS
Scaling by the End of the Roadmap and Beyond featuring Thin Films, Nanowires
and Heterogeneous Integration on Silicon”
17:00 K. Yamada (Waseda Univ.) “Fabrication of Si nanowire FETs and
their characteristics” 17:30 T.
Hiramoto (Univ. Tokyo) “ Mobility and strain characteristics in silicon
nanowire FETs” 18:00 C. Claeys
(IMEC) “Fabrication and
Characterization of Si and Heterojunction Tunnel Field Effect Transistors”
18:30-20:30 Reception at Royal Blue Hall
Wednesday,
14 October
Session
3
9:45 S. Takagi (Univ. Tokyo) “New channel material MOSFETs on Si platform”
10:15 Y. Miyamoto (Tokyo Tech.) “InGaAs/InP MISFET”
10:45 T. Ando (Tokyo Tech.) “Theory of graphene and carbon
nanotubes”
11:15 W.I. Milne (Cambridge Univ. U.K.) “CNTs vs SiNWs for future electronics”
11:45 K. Banerjee (Univ. California at Santa
Barbara, U.S.A.) “Carbon based active and passive devices for next-generation
ICs”
12:30 Lunch Break
Session
4
13:15 S. Oda (Tokyo Tech.) “Silicon quantum dots and related
devices”
13:45 N. Koshida (Tokyo Univ. Agri. &
Tech.) “Application of Si
nanocrystals”
14:15 D. Williams (Hitachi Cambridge Lab.
U.K.) “Structures for Quantum
Computing Using Coupled Silicon Quantum Dots”
14:45 S. Sugahara (Tokyo Tech.) “Spin-functional MOSFETs”
15:15 K. Uchida (Tokyo Tech.) “Trends and prospects of Si devices for
LSI applications”
15:45 Break and Poster session
16:30 Panel Discussion: Si nanodevices in 2030
18:30 H. Ishiwara (Tokyo
Tech.) Closing Remarks and Best
Poster Awards Presentation
18:45 Wrap up
Poster
Session (October 13, Tuesday, 15:00~15:30, October 14, Wednesday, 15:45~16:30 )
P-1. Gento Yamahata, Tetsuo Kodera, Hiroshi
Mizuta, Ken Uchida, and Shunri
Oda:
“Electron transport through coupled Si quantum dots toward quantum information
devices”
P-2. J. Ogi, T. Ferrus, T. Kodera, Y.
Tsuchiya, K. Uchida, D. A. Williams, H. Mizuta and S. Oda: “Suspended quantum
dot devices for sensor or quantum bit applications”
P-3. T. Nagami, Y. Tsuchiya, K. Uchida, H.
Mizuta, and S. Oda: “Scaling Analysis of NEMS Memory Devices”
P-4. Y.Nakamine, T. Kodera, K. Uchida and S.
Oda: “Phosphorous-Doping in Silicon Nanocrystals by using VHF Plasma”
P-5. Chao Yan, Ken Uchida and Shunri Oda:
“Design Optimization of
MEMS(NEMS)
Resonator by 3-D Anisotropic Thermoelastic Modeling”
P-6. Berrin Pinar Algul, Ken Uchida, Shunri
Oda: “Modeling of Band-to- Band Tunneling in MOS Structures”
P-7. Jean L. Tarun, Shaoyun Huang, Ken
Uchida, Naoki Fukata, Koji Ishibashi and Shunri Oda: “Transport Properties of
Silicon Nanowire with Ferromagnetic Leads”
P-8. Ian C. Robertson, Ken Uchida and Shunri
Oda: “Artificial Membrane Interfacial Layers via 1D nanostructures for
Bio-Sensors”
P-9. Liang HE, Koichi Usami, Ken Uchida and
Shunri Oda: “Preparation and characterization of P-doped Ge nanowires by
VLS-CVD”
P-10.
T. Kodera, G. Yamahata, T. Kambara, T. Ferrus, D. A. Williams, K.
Uchida,
Y. Arakawa, S. Oda: “Fabrication and characterization of silicon double quantum
dots towards spin qubits”
P-11.
Xin Zhou, Ken Uchida and Shunri Oda: “Carrier transport in ensemble of Si
nanocrystals prepared by VHF plasma process”
P-12.
Tetsuya Ishikawa, Hiroki Nikaido, Koichi Usami, Ken Uchida, Shunri
Oda:
“Formation of two-dimensional array of Si nanocrystals using nano Si ink”
P-13.
D. Hippo, Y. Nakamine, K. Uchida, and S. Oda: “Thermotherapy for Cancer Using
Silicon Nanocrystals”
P-14.
Hisashi Saito, Yasuyuki Miyamoto, and Kazuhito Furuya: “Fabrication of vertical
InGaAs channel MISFET with heterostructure launcher and undoped channel”
P-15.
Kazuya Wakabayashi, Toru Kanazawa, Hisashi Saito, Ryosuke Terao, Shunsuke
Ikeda, Yasuyuki Miyamoto and Kazuhito Furuya: “InP/In0.53Ga0.47As composite
channel n-MOSFET with heavily doped regrown source/drain structure”
P-16.
Yasuo Azuma, Yuhsuke Yasutake, Keijiro Kono, Xinheng Li, Masayuki Kanehara,
Toshiharu Teranishi, Simon Chorley, Charles G. Smith and Yutaka
Majima:
“Single-electron transistors by stable chemisorbed Au nanoparticle”
P-17.
Victor M. Serdio V., Seiichi Suzuki, Shinya Kano, Taro Muraki, Yasuo Azuma,
Masayuki Kanehara, Toshiharu Teranishi, and Yutaka Majima: “Self- termination
Process in Electroless Au Plating of Electrodes towards Nanogap based Single
Electron Transistors”
P-18.
Kenichi Matsunaga, Toshiaki Yamagishi, Masaya Miyahara, Akira
Matsuzawa:
“ An Ultra-Low Power Wireless Communication Circuit for Medical Telemetry
Applications”
P-19.
Daehwa Paik, Hyunui Lee, Kei Yoshihara, Tatsuya Urano, Masaya Miyahara, and
Akira Matsuzawa: “High-Speed Analog-to-Digital Converters for mm-Wave
Transceivers”
P-20.
Vu Minh Khoa, Fei li, Masaya Miyahara, and Akira Matsuzawa: “Qpix, A Pixel
Readout LSI with a Built-in ADC for Particle Detector Applications”
P-21.
Tuan Minh Vo, Masaya Miyahara, and Akira Matsuzawa: “A 10-bit, 290 fJ/conv.
Steps, 0.13 mm2, Zero-Static Power, Self Clocking Capacitance to Digital
Converter”
P-22.
Ning Li, Shogo Ito, Kota Matsushita, Naoki Takayama, Kenichi Okada and Akira
Matsuzawa: “A 60GHz CMOS RF Front-end for Gbps Wireless Communication”
P-23.
Ahmed Musa, Win Chaivipas, Kouyou Sato, Rui Murakami, Shoichi Hara, Kenichi
Okada, and Akira Matsuzawa: “A Low-Phase-Noise Frequency Synthesizer for 60GHz
Wireless Transceivers Using a 65nm CMOS process”
P.-24.
Abdeldjelil Habib Zahmani, Akira Nishijima, Sang Yoon Park, and Adarsh Sandhu:
“Hybrid AlGaN/GaN- ZnO nanowire devices for environmental monitoring”
P-25.
Y. Morimoto, S.Y. Park, S. Sakamoto, H. Handa and A. Sandhu: “ Detection of
sub-100nm diameter superparamagnetic targets by magnetic self- assembly for
point of care bio-diagnosis”
P-26.
M. K. Bera, J. Song, P. Ahmet, K. Kakushima, K. Tsutsui, A.
Nishiyama,
N. Sugii, T. Hattori, H. Iwai: “Rare-earth based mixed oxide as high-k gate
dielectrics for Ge MOSFET”
P-27.
J. Song, K. Kakushima, P. Ahmet, K. Tsutsui, N. Sugii, T. Hattori and H. Iwai:
“Effect of Ultrathin Si Passivation Layer for La2O3/Ge MOS structure”
P-28.
T. Kawanago, K. Kakushima, P.Ahmet, K.Tsutsui, A. Nishiyama, N.
Sugii,
K. Natori, T. Hattori, H. Iwai: “Experimental Investigation of VFB shift and
Effective Mobility in La2O3 MOS Devices”
P-29.
Soshi Sato, Hideaki Arai, Kuniyuki Kakushima, Parhat Ahmet and Hiroshi Iwai:
“Evaluation of Channel Potential Profile of Si Nanowire Field Effect
Transistor”
P-30.
M. Mamatrishat, M. Kouda, K. Kakushima, P. Ahmet, K. Tsutsui, N.
Sugii,
K. Natori, T. Hattori, H. Iwai: “Study on Remote Coulomb Scattering Limited
Mobility in MOSFETs with CeO2/ La2O3 Gate Stacks”
P-31.
A. Abudukelimu, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N.
Sugii,
K. Natori, T. Hattori, H. Iwai: “Current-Voltage Characteristics of Ballistic
Nanowire MOSFET by Numerical Analysis”
P-32.
M. Kouda, N. Umezawa, K. Kakushima, H. Nohira, P. Ahmet, K.
Shiraishi,
T. Chikyow, K. Yamada, H. Iwai: “Charged defects reduction in gate insulator
with multivalent materials”
P-33.
Yeonghun Lee, Kuniyuki Kakushima, Kenji Shiraishi, Kenji Natori and Hiroshi
Iwai: “Size-Dependent Transport Characteristics of Ballistic Silicon Nanowire
FETs”
P-34.
H. Nakayama, K. Kakushima, P. Ahmet, E. Ikenaga,K. Tsutsui, N. Sugii, T.
Hattori and H. Iwai: “Crystallographic Orientation Dependent Electrical
Characteristics of La2O3 MOS Capacitors”
P-35.
H. Arai, H. Kamimura, S. Sato, K. Kakushima, P. Ahmet, A. Nishiyama, K.
Tsutsui, N. Sugii, K. Natori, T. Hattori and H. Iwai: “Annealing Reaction for
Ni Silicidation of Si Nanowire”
P-36.
K. Funamizu, T. Kanda, Y.C. Lin, K. Kakushima, P. Ahmet, K. Tsutsui, A.
Nishiyama, N. Sugii, E.Y. Chang, K. Natori, T. Hattori and H. Iwai: “
Electrical Characteristics of HfO2 and La2O3 Gate Dielectrics for In0.53Ga0.
47As
MOS Structure”
P-37.
W.Hosoda, K.Ozawa, K.Kakushima, P.Ahmet, K.Tsutsui, A.Nishiyama, N.
Sugii,
K.Natori, T.Hattori, and H.Iwai: “A Study of Schottky Barrier Height Modulation
of NiSi by Interlayer Insertion and Its Application to SOI SB-MOSFETs”
P-38.
K. Matano, K. Kakushima, P. Ahmet, N. Sugii, K. Tsutsui, T. Hattori, and H.
Iwai: “Threshold Voltage Control in p-MOSFET with High-k Gate dielectric”
P-39.
T. Koyanagi, K. Kakushima, P. Ahmet, K. Tsutsui,A. Nishiyama, N.
Sugii,
K. Natori, T. Hattori, and H. Iwai: “Influence of Alkali Earth Elements Capping
on Electrical Characteristics of La2O3 Gated MOS Device”
P-40.
Y. Kobayashi, K. Kakushima, P. Ahmet, V. Ramgopal Rao, K. Tsutsui and H. Iwai:
“Short-channel effects on FinFETs induced by inappropriate fin widths”
P-41.
Keita Takahashi, Takao Oshita and Kazuo Tsutsui: “Growth of fluoride
heterostructures on Ge (111) for Si-based resonant tunnelling devices”
P-42.
Jumpei Ishikawa, Jun Gao, and Shun-ichiro Ohmi: “Work Function Modulation of
PtSi by Alloying with Yb”
P-43.
Jun Gao, Jumpei Ishikawa, and Shun-ichiro Ohmi: “Improvement of Thermal
Stability for PtSi Alloying with Hf Utilizing Two-Step Silicidation Process”
P-44.
T. Sano and S. Ohmi: “HfON Formation on 3-Dimentional Structure Utilizing ECR
Sputtering”
P-45.
Y-U Song, S. Ohmi and H. Ishiwara: “Electrical characteristics of
pentacene-based OFETs with thin gate dielectric”
P-46.
Jeong Hwan Kim, Hiroshi Funakubo, Sugiyama Yoshihiro, and Hiroshi
Ishiwara:
“Charateristics of Undoped And Mn-doped BiFeO3 Films Formed on Pt and SrRuO3/Pt
Electrodes by RF sputtering”
P-47.
Joo-Won Yoon, Sung-Min Yoon, and Hiroshi Ishiwara: “Comparative study on MFIS
(metal-ferroelectric-insulator-semiconductor) diodes composed of P(VDF-TrFE)
and PMMA(poly methyl metacrylate)-blended P(VDF-TrFE) ”
P-48.
Yota Takamura and Satoshi Sugahara: “Half-metallic ferromagnet technologies for
spin-functional MOSFETs”
P-49.
Y. Shuto, R. Nakane, H. Sukegawa, S. Yamamoto, M. Tanaka, K. Inomata, and S.
Sugahara: “Fabrication and characterization of pseudo-spin-MOSFETs”
P-50.
Shuu’ichirou Yamamoto, Yusuke Shuto, and Satoshi Sugahara: “ Nonvolatile
power-gating microprocessor concepts using nonvolatile SRAM and flip-flop”
P-51.
A.Teranishi, S.Suzuki and M.Asada: “Resonant Tunneling Diode with Very High
Peak Current Density for Terahertz Oscillators”
P-52.
Takumi Uezono, Takashi Sato, and Kazuya Masu: “A Time-Slicing Ring Oscillator
for Capturing Time-Dependent Delay Degradation and Power Supply Voltage
Fluctuation”
P-53.
Shiho HAGIWARA, Takumi UEZONO, Takashi SATO and Kazuya MASU: “ Improvement of
Power Distribution Network using Correlation-based Regression Analysis”
P-54.
Tomoaki Maekawa, Shuhei Amakawa, Noboru Ishihara, and Kazuya Masu: “ High-Speed
and Low-Power On-Chip Transmission Line Interconnect Technologies”
P-55.
Sang_yeop Lee, Tomoya Nakajima, Shuhei Amakawa, Noboru Ishihara, and Kazuya
Masu: “Scalable Wideband RF LNA and VCO based on CMOS Inverter Topologies P-56.
Jun-Ichi Iwata, Kenji Shiraishi, Atsushi Oshiyama: “First-principles calculations
for Si nanowires in nano-meter diameters”
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EDS Japan Chapter連絡先:Secretary 田中 徹
E-mail:ttanaka@ieee.org
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page:http://www.ieee-jp.org/section/tokyo/chapter/ED-15/
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