IEEE SSCS Kansai Chapter Technical Seminar

IEEE SSCS Kansai Chapterでは，下記の日程で技術セミナーを開催致しました．
今回はSymposia on VLSI Technology/Circuits 国内報告会として, 2021 Symposia on VLSI Technology/Circuits で講演された17名の方からご講演いただきました．

日時
2021年7月30日（金）10:00より16:40

会場
オンライン

主催
IEEE Solid-State Circuits Society Kansai Chapter, IEEE Electron Devices Society Kansai Chapter

共催
IEEE Solid-State Circuits Society Japan Chapter, IEEE Electron Devices Society Japan Chapter

講演

10:00-10:05 Opening Kazutoshi Kobayashi (Kyoto Institute of Technology)

10:05-10:20 VLSI Symposia Review Yusuke Oike (Sony), Katsura Miyashita (Toshiba)

10:20-10:25 ISSCC 2022 Call for Papers Jun Deguchi (Kioxia), Munehiko Nagatani (NTT)

Session 1 (Chair: Takashi Hashimoto (Panasonic))

10:25-10:40 A 6.78 MHz Wireless Power Transfer System for Simultaneous Charging of Multiple Receivers with Maximum Efficiency using Adaptive Magnetic Field Distributor IC Hao Qiu (The University of Tokyo)

10:40-10:55 On-Silicon Photonic Integrated Circuit toward On-Chip Interconnection and Distributed Computing Nobuhiko Nishiyama (Tokyo Institute of Technology)

10:55-11:10 A 28-GHz Phased-Array Relay Transceiver for 5G Network Using Vector-Summing Backscatter with 24-GHz Wireless Power and LO Transfer Michihiro Ide (Tokyo Institute of Technology)

11:10-11:25 A Fast-Beam-Switching 28-GHz Phased-Array Transceiver Supporting Cross-Polarization Leakage Self-Cancellation Jian Pang (Tokyo Institute of Technology)

11:25-11:40 A 0.186-pJ per Bit Latch-Based True Random Number Generator with Mismatch Compensation and Random Noise Enhancement Ruilin Zhang (Waseda University )

11:40-11:55 Breakout session (QA session)

11:55-13:00 Lunch break

Session 2 (Chair: Mutsunori Uenuma (NAIST))

13:00-13:15 A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with -80-dBc Reference Spur Zule Xu (The University of Tokyo)

13:15-13:30 Superconducting Quantum Computer: a Hint for Building Architectures Yutaka Tabuchi (The Univ. of Tokyo)

13:30-13:45 Buried Nanomagnet Realizing High-Speed/Low-Variability Silicon Spin Qubits: Implementable in Error-Correctable Large-Scale Quantum Computers Shota Iizuka (AIST)

13:45-14:00 A CMOS Image Sensor and an AI Accelerator for Realizing Edge-Computing-Based Surveillance Camera Systems Norihito Kato (Renesas Electronics Corporation)

14:00-14:15 Strategy toward HZO BEOL-FeRAM with Low-Voltage Operation (≤ 1.2 V), Low Process Temperature, and High Endurance by Thickness Scaling Kasidit Toprasertpong (The Univ. of Tokyo)

14:15-14:30 Critical Role of GIDL Current for Erase Operation in 3D Vertical FeFET and Compact Long-Term FeFET Retention Model Masaharu Kobayashi (The Univ. of Tokyo)

14:30-14:45 Breakout session (QA session)

14:45-14:50 IMFEDK/IRPS Call for Papers Mutsumi Kimura (Ryukoku Univ.), Kazutoshi Kobayashi (Kyoto Institute of Technology)

Session 3 (Chair: Mutsumi Kimura (Ryukoku Univ.))

14:50-15:05 Analog In-Memory Computing in FeFET-Based 1T1R Array for Edge AI Applications Daisuke Saito (Sony Semiconductor Solutions)

15:05-15:20 Energy-Efficient Reliable HZO FeFET Computation-in-Memory with Local Multiply & Global Accumulate Array for Source-Follower & Charge-Sharing Voltage Sensing Chihiro Matsui (The Univ. of Tokyo)

15:20-15:35 Chiplet-Based Advanced Packaging Technology from 3D/TSV to FOWLP/FHE Takafumi Fukushima (Tohoku Univ.)

15:35-15:50 3-Dimensional Integration of Epitaxial Magnetic Tunnel Junctions with New Materials for Future MRAM Shinji Yuasa (AIST)

15:50-16:05 3D Stacked CIS Compatible 40nm Embedded STT-MRAM for Buffer Memory Mikio Oka (Sony Semiconductor Solutions)

16:05-16:20 Impact of Asymmetric Strain on Performance of Extremely-Thin Body (100) GOI and (110) SGOI pMOSFETs Chia Tsong Chen (The Univ. of Tokyo)

16:20-16:25 Closing Hirobumi Watanabe (Ricoh)

16:25-16:40 Breakout session (QA session)

参加者
147名

Last modified: Aug. 2, 2021

日時	2021年7月30日（金）10:00より16:40
会場	オンライン
主催	IEEE Solid-State Circuits Society Kansai Chapter, IEEE Electron Devices Society Kansai Chapter
共催	IEEE Solid-State Circuits Society Japan Chapter, IEEE Electron Devices Society Japan Chapter
講演
	10:00-10:05	Opening	Kazutoshi Kobayashi (Kyoto Institute of Technology)
	10:05-10:20	VLSI Symposia Review	Yusuke Oike (Sony), Katsura Miyashita (Toshiba)
	10:20-10:25	ISSCC 2022 Call for Papers	Jun Deguchi (Kioxia), Munehiko Nagatani (NTT)
	Session 1 (Chair: Takashi Hashimoto (Panasonic))
	10:25-10:40	A 6.78 MHz Wireless Power Transfer System for Simultaneous Charging of Multiple Receivers with Maximum Efficiency using Adaptive Magnetic Field Distributor IC	Hao Qiu (The University of Tokyo)
	10:40-10:55	On-Silicon Photonic Integrated Circuit toward On-Chip Interconnection and Distributed Computing	Nobuhiko Nishiyama (Tokyo Institute of Technology)
	10:55-11:10	A 28-GHz Phased-Array Relay Transceiver for 5G Network Using Vector-Summing Backscatter with 24-GHz Wireless Power and LO Transfer	Michihiro Ide (Tokyo Institute of Technology)
	11:10-11:25	A Fast-Beam-Switching 28-GHz Phased-Array Transceiver Supporting Cross-Polarization Leakage Self-Cancellation	Jian Pang (Tokyo Institute of Technology)
	11:25-11:40	A 0.186-pJ per Bit Latch-Based True Random Number Generator with Mismatch Compensation and Random Noise Enhancement	Ruilin Zhang (Waseda University )
	11:40-11:55	Breakout session (QA session)
	11:55-13:00	Lunch break
	Session 2 (Chair: Mutsunori Uenuma (NAIST))
	13:00-13:15	A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with -80-dBc Reference Spur	Zule Xu (The University of Tokyo)
	13:15-13:30	Superconducting Quantum Computer: a Hint for Building Architectures	Yutaka Tabuchi (The Univ. of Tokyo)
	13:30-13:45	Buried Nanomagnet Realizing High-Speed/Low-Variability Silicon Spin Qubits: Implementable in Error-Correctable Large-Scale Quantum Computers	Shota Iizuka (AIST)
	13:45-14:00	A CMOS Image Sensor and an AI Accelerator for Realizing Edge-Computing-Based Surveillance Camera Systems	Norihito Kato (Renesas Electronics Corporation)
	14:00-14:15	Strategy toward HZO BEOL-FeRAM with Low-Voltage Operation (≤ 1.2 V), Low Process Temperature, and High Endurance by Thickness Scaling	Kasidit Toprasertpong (The Univ. of Tokyo)
	14:15-14:30	Critical Role of GIDL Current for Erase Operation in 3D Vertical FeFET and Compact Long-Term FeFET Retention Model	Masaharu Kobayashi (The Univ. of Tokyo)
	14:30-14:45	Breakout session (QA session)
	14:45-14:50	IMFEDK/IRPS Call for Papers	Mutsumi Kimura (Ryukoku Univ.), Kazutoshi Kobayashi (Kyoto Institute of Technology)
	Session 3 (Chair: Mutsumi Kimura (Ryukoku Univ.))
	14:50-15:05	Analog In-Memory Computing in FeFET-Based 1T1R Array for Edge AI Applications	Daisuke Saito (Sony Semiconductor Solutions)
	15:05-15:20	Energy-Efficient Reliable HZO FeFET Computation-in-Memory with Local Multiply & Global Accumulate Array for Source-Follower & Charge-Sharing Voltage Sensing	Chihiro Matsui (The Univ. of Tokyo)
	15:20-15:35	Chiplet-Based Advanced Packaging Technology from 3D/TSV to FOWLP/FHE	Takafumi Fukushima (Tohoku Univ.)
	15:35-15:50	3-Dimensional Integration of Epitaxial Magnetic Tunnel Junctions with New Materials for Future MRAM	Shinji Yuasa (AIST)
	15:50-16:05	3D Stacked CIS Compatible 40nm Embedded STT-MRAM for Buffer Memory	Mikio Oka (Sony Semiconductor Solutions)
	16:05-16:20	Impact of Asymmetric Strain on Performance of Extremely-Thin Body (100) GOI and (110) SGOI pMOSFETs	Chia Tsong Chen (The Univ. of Tokyo)
	16:20-16:25	Closing	Hirobumi Watanabe (Ricoh)
	16:25-16:40	Breakout session (QA session)
参加者	147名