IEEE SSCS Kansai Chapter Technical Seminar

IEEE SSCS Kansai Chapterでは，下記の日程で技術セミナーを開催致しました．
今回はInternatioal Solid-State Circuits Conference (ISSCC) 2017報告会でした．
2017年2月のISSCC（サンフランシスコ，米国）で発表された注目論文を，12名の方 からご講演いただきました．

日時	2017年2月17日（金）9:30より17:20
会場	神戸大学・梅田インテリジェントラボラトリ; 講義室． Access Map
主催	IEEE Solid-State Circuits Society Kansai Chapter
共催	IEEE Solid-State Circuits Society Japan Chapter ISSCC Far-East Regional Committee 神戸大学大学院システム情報学研究科
講演
	9:30-9:35	Opening SSCS Kansai Chapter Chair, Prof. Makoto Nagata
	9:35-10:00	ISSCC 2017 レビュー講演 Dr. Atsuki Inoue, Fujitsu Lab. Ltd.　 ISSCC Far-East Regional Committee Chair
	10:00-10:30	Lecture 1 (Imagers分野), 4.3 "A Programmable Sub-Nanosecond Time-Gated 4-Tap Lock-In Pixel CMOS Image Sensor for Real-Time Fluorescence Lifetime Imaging Microscopy" M-W. Seo, Y. Shirakawa, Y. Masuda, Y. Kawata, K. Kagawa, K. Yasutomi, S. Kawahito Shizuoka University, Hamamatsu, Japan
	10:30-11:00	Lecture 2 (Imagers分野), 4.8 "A 0.44erms Read-Noise 32fps 0.5Mpixel High-Sensitivity RG-Less-Pixel CMOS Image Sensor Using Bootstrapping Reset" M-W. Seo 1, T. Wang 1, S-W. Jun 2, T. Akahori 2, S. Kawahito 1,2 1 Shizuoka University, Hamamatsu, Japan 2 Brookman Technology, Hamamatsu, Japan
	11:00-11:30	Lecture 3 (Innovations in Technologies and Circuits分野), 15.8 "A Permanent Digital Archive System Based on 4F2 X-Point Multi-Layer Metal Nano-Dot Structure" N. Miura, S. Liu, T. Watanabe, S. Imai, M. Nagata Kobe University, Kobe, Japan
	11:30-12:00	Lecture 4 (Imagers分野), 4.6 "A 1/2.3in 20Mpixel 3-Layer Stacked CMOS Image Sensor with DRAM" T. Haruta 1, T. Nakajima 1, J. Hashizume 1, T. Umebayashi 1, H. Takahashi 1, K. Taniguchi 1, M. Kuroda 1, H. Sumihiro 1, K. Enoki 1, T. Yamasaki 2, K. Ikezawa 1, A. Kitahara 1, M. Zen 1, M. Oyama 1, H. Koga 1, H. Tsugawa 1, T. Ogita 1, T. Nagano 1, S. Takano 3, T. Nomoto 1 1 Sony Semiconductor Solutions, Atsugi, Japan 2 Sony Semiconductor Manufacturing, Atsugi, Japan 3 Sony LSI Design, Atsugi, Japan
	12:00-12:30	Lecture 5 (Imagers分野), 4.9 "A 1ms High-Speed Vision Chip with 3D-Stacked 140GOPS Column-Parallel PEs for Spatio-Temporal Image Processing" T. Yamazaki 1, H. Katayama 1, S. Uehara 1, A. Nose 1, M. Kobayashi 1, S. Shida 1, M. Odahara 2, K. Takamiya 2, Y. Hisamatsu 2, S. Matsumoto 2, L. Miyashita 3, Y. Watanabe 3, T. Izawa 1, Y. Muramatsu 1, M. Ishikawa 3 1 Sony Semiconductor Solutions, Atsugi, Japan 2 Sony LSI Design, Atsugi, Japan 3 University of Tokyo, Bunkyo, Japan
	12:30-13:45	Lunch
	13:45-14:15	Lecture 6 (Nonvolatile Memory Solutions分野), 11.1 "A 512Gb 3b/cell 3D NAND Flash Memory on 64-Word-Line-Layer Technology" R. Yamashita 1, S. Magia 1, T. Higuchi 2, K. Yoneya 2, T. Yamamura 2, H. Mizukoshi 1, S. Zaitsu 1, M. Yamashita 1, S. Toyama 1, N. Kamae 1, J. Lee 1, S. Chen 1, J. Tao 1, W. Mak 1, X. Zhang 1, Y. Yu 1, Y. Utsunomiya 2, Y. Kato 1, M. Sakai 1, M. Matsumoto 1, H. Chibvongodze 1, N. Ookuma 1, H. Yabe 1, S. Taigor 1, R. Samineni 1, T. Kodama 2, Y. Kamata 2, Y. Namai 2, J. Huynh 1, S-E. Wang 1, Y. He 1, T. Pham 1, V. Saraf 1, A. Petkar 1, M. Watanabe 1, K. Hayashi 1, P. Swarnkar 1, H. Miwa 1, A. Pradhan 1, S. Dey 1, D. Dwibedy 1, T. Xavier 1, M. Balaga 1, S. Agarwal 1, S. Kulkarni 1, Z. Papasaheb 1, S. Deora 1, P. Hong 1, M. Wei 1, G. Balakrishnan 1, T. Ariki 1, K. Verma 1, C. Siau 1, Y. Dong 1, C-H. Lu 1, T. Miwa 1, F. Moogat 1 1 Western Digital, Milpitas, CA 2 Toshiba, Yokohama, Japan
	14:15-14:45	Lecture 7 (Digital Processors分野), 3.5 "A 40nm Flash Microcontroller with 0.80&[mu]s Field-Oriented-Control Intelligent Motor Timer and Functional Safety System for Next-Generation EV/HEV" H. Kimura 1, H. Noda 1, H. Watanabe 1, T. Higuchi 1, R. Kobayashi 2, M. Utsuno 1, F. Takami 1, S. Otani 1, M. Ito 1, Y. Shimazaki 1, N. Yada 1, H. Kondo 1 1 Renesas Electronics, Tokyo, Japan 2 Renesas System Design, Tokyo, Japan
	14:45-15:15	Lecture 8 (Biomedical Circuits分野), 27.6 "Single-Chip 3072ch 2D Array IC with RX Analog and All-Digital TX Beamformer for 3D Ultrasound Imaging" Y. Katsube 1, S. Kajiyama 2, T. Nishimoto 1, T. Nakagawa 2, Y. Okuma 3, Y. Nakamura 2, T. Terada 2, Y. Igarashi 1, T. Yamawaki 2, T. Yazaki 1, Y. Hayashi 2, K. Amino 2, T. Kaneko 2, H. Tanaka 2 1 Hitachi, Yokohama, Japan 2 Hitachi, Kokubunji, Japan 3 Hitachi, Hatoyama, Japan
	15:15-15:45	Lecture 9 (Digital PLLs and Security Circuits分野), 8.5 "A 0.42ps Jitter -241.7dB-FOM Synthesizable Injection-Locked PLL with Noise-Isolation LDO" H. C. Ngo, K. Nakata, T. Yoshioka, Y. Terashima, K. Okada, A. Matsuzawa Tokyo Institute of Technology, Tokyo, Japan
	15:45-16:00	Break
	16:00-16:30	Lecture 10 (TX and RX Building Blocks分野), 17.9 "A 105Gb/s 300GHz CMOS Transmitter" K. Takano 1, S. Amakawa 1, K. Katayama 1, S. Hara 2, R. Dong 2, A. Kasamatsu 2, I. Hosako 2, K. Mizuno 3, K. Takahashi 3, T. Yoshida 1, M. Fujishima 1 1 Hiroshima University, Higashihiroshima, Japan 2 National Institute of Information and Communications Technology, Koganei, Japan 3 Panasonic, Yokohama, Japan
	16:30-16:45	Lecture 11 (Wireless Receivers and Synthesizers分野), 24.9 "A 128-QAM 60GHz CMOS Transceiver for IEEE802.11ay with Calibration of LO Feedthrough and I/Q Imbalance" J. Pang, S. Maki, S. Kawai, N. Nagashima, Y. Seo, M. Dome, H. Kato, M. Katsuragi, K. Kimura, S. Kondo, Y. Terashima, H. Liu, T. Siriburanon, A. T. Narayanan, N. Fajri, T. Kaneko, T. Yoshioka, B. Liu, Y. Wang, R. Wu, N. Li, K. K. Tokgoz, M. Miyahara, K. Okada, A. Matsuzawa Tokyo Institute of Technology, Tokyo, Japan
	16:45-17:15	Lecture 12 (Hybrid ADCs分野), 28.7 "A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm CMOS with Digital Amplifier Technique" K. Yoshioka, T. Sugimoto, N. Waki, S. Kim, D. Kurose, H. Ishii, M. Furuta, A. Sai, T. Itakura Toshiba, Kawasaki, Japan
	17:15-17:20	Closing
	参加者	41名（IEEE Member：23名、Non-Member：18名）
	講演者と役員