第5回関西コロキアム・電子デバイスワークショップ開催報告

開催日時：2005年10月26日(水) 10:00〜17:00
開催場所：大阪大学中之島センター 10Ｆ 佐治敬三メモリアルホール
公用語:日本語
プログラム
[10:00 - 10:10]　開会挨拶　谷口研二(大阪大学)
[10:10 - 11:25] セッションI．Silicon and Compound Semiconductor Device Technology
座長：龍見雅美（住友電気工業）
[10:10-10:35]
#1 Design and Fabrication of RESURF MOSFETs on 4H-SiC(0001), (1120), and 6H-SiC(0001)
T. Kimoto, H. Kosugi, J. Suda, Y. Kanzaki, H. Matsunami(Department of Electronic Science and Engineering, Kyoto University.)
[10:35-11:00]
#2 Test Structure Measuring Inter- and Intra-layer Coupling Capacitance of Interconnection with Sub-femto Farad Resolution
T. Kunikiyo, T. Watanabe, T. Kanamoto, H. Asazato, M. Shirota, K. Eikyu, Y. Ajioka, H. Makino, K. Ishikawa, S. Iwade, and Y. Inoue (Renesas Technology Corporation)
[11:00-11:25]
#3 350V/150A AlGaN/GaN Power HFET on Silicon Substrate with Source-via Grounding (SVG) Structure
M. Hikita, M. Yanagihara, K. Nakazawa, H. Ueno, Y. Hirose, T. Ueda, Y. Uemoto, T. Tanaka, D. Ueda, and T. Egawa (Matsushita Electric)

―昼食 [11:25 - 12: 45]―

[12:45 -13:35]セッションIIA．Device, Process and Material Technology
座長：大村泰久（関西大学）
[12:45-13:10]
#1 Direct Measurement of Stress Dependent Inversion Layer Mobility Using a Novel Test Structure
T. Okagaki, M. Tanizawa, T. Uchida, T. Kunikiyo, K. Sonoda, M. Igarashi, K. Ishikawa, T. Takeda*, P. Lee*, and G. Yokomizo* (Renesas Technology Corp.[Hyogo] *Renesas Technology Corp.[Tokyo])
[13:10-13:35]
#2 Charge-Injection Length in Silicon Nanocrystal Memory Cells
T. Osabe, T. Ishii, T. Mine, T. Sano*, T. Arigane, T. Fukumura**, H. Kurata, S. Saeki*, Y. Ikeda**, K. Yano (Central Research Laboratory, Hitachi, ltd., *Renesas Northern Japan Semiconductor Inc. **Renesas Technology Corp.)

―休憩 [13:35 - 13:50]―

[13:50 - 15:30]セッションIIB．Device, Process and Material Technology
座長：渡辺博文（リコー）
[13:50-14:15]
#3 High Performance of InGaN LEDs on (111) Silicon Substrates Grown by MOCVD
T. Egawa, B. Zhang, and H. Ishikawa (Research Center for Nano-Device and Systems, Nagoya Institute of Technology.)
[14:15-14:40]
#4 Detailed Investigation of Geometrical Factor for Pseudo-MOS Transistor Technique
K. Komiya*#, N. Bresson*, S. Sato, S. Cristoloveanu*, and Y. Omura (High-Technology Research Center, Kansai University. *IMEP(UMR CNRS-INPG-UJF), #presently Sharp Corp.)
[14:40-15:05]
#5 Simulation of Characteristics of a SiO2/c-axis-oriented LiNbO3/diamond Surface Acoustic Wave
S. Shikata*#, A. Hachigo*, and H. Nakahata* (*Sumitomo Electr. Ind. Ltd., Itami., #presently AIST, Tsukuba)
[15:05-15:30]
#6 Successful Enhancement of Lifetime for SiO2 on 4H-SiC by N2 Anneal
K. Fujihira, N. Miura, K. Shizawa, M. Imaizumi, K. Otsuka and T.Takami (Mitsubishi Electric.)

―休憩 [15:30 - 15:45]―

[15:45 - 16:35]セッションIII．Silicon LSI Technology
座長：小瀧浩（シャープ）
[15:45-16:10]
#1 Soft Error Free, Low Power and Low Cost Super SRAM with 0.98um2 Cell By Utilizing Existing 0.15um-DRAM Process
Y. Fujii, Y. Ishigaki, T. Hosokawa, M. Dei, Y. Maki, A. Nishida, T. Izutsu*, and Y. Kihara (LSI Manufacturing Technology Unit, Renesas Technology Corp. *Memory Design Department, Renesas Technology Corp.)
[16:10-16:35]
#2 A 0.13um MRAM with 0.26x0.44um2 MTJ Optimized on Universal MR-RA Relation for 1.2 V High-Speed Operation beyond 143 MHz
S. Ueno, T. Eimori, T. Kuroiwa**, H. Furuta, J. Tsuchimoto, S. Maejima, S. Iida, H. Ohshita, S. Hasegawa, S. Hirano, T. Yamaguchi, H. Kurisu, A. Yutani, N. Hashikawa, H. Maeda, Y. Ogawa, K. Kawahata, Y. Ohmura, T. Tsuji*, J. Ohtani*, T. Tanizaki***, Y. Yamaguchi*, T. Ohishi*, H. Hidaka*, T. Takenaga**, S. Beysen**, H. Kobayashi**, T. Oomori**, T. Koga and Y. Ohji (Renesas Technology, *Renesas Technology, ***Renesas Device Design Corporation, **Mitsubishi Electric)

[16:35-17:00] AWARD授与
―閉会― 谷口研二(大阪大学)
MFSK(Message from Spirited Kansai)Award受賞者
・木本 恒暢 先生(京都大学)
・小宮健治 様(関西大学、現在、シャープ)
・藤井康博 様(ルネサステクノロジ)(受取代理:牧幸生 様)