第２回関西コロキアム電子デバイスワークショップ

（第2回　MFSK　Award　選考会）

主催：IEEE　Electron　Devices　Society　Kansai　Chapter

共催：大阪大学工学部,京都大学エネルギー科学研究科

日時：平成14年7月11日（木）午後1時〜午後5時05分

会場：大阪大学コンベンションセンター第2会議室

場所：吹田市山田丘（末尾参照）

定員：100名

公用語：日本語

会費：無料

使用機器：OHPおよびProjector共に可

講演時間配分：一件につき発表２０分、質疑応答5分

問い合わせ先：京都大学　山本靖　（　yasushi@iae.kyoto-u.ac.jp　）

Advance　Program

Opening Session Chaired by Y. Yamamoto (kyoto Univ.)

1:00pm Opening Remark by H. Nozawa(kyoto Univ.)

1:05pm Award Presentation by T. Nishimura (Mitsubishi)

Technical Session A Chaired by Y. Inoue (Mitsubishi)

1:10pm A-1,”Lithography Solution for 65-nm Node System LSIs”

T. Matsuo, M. Endo, S. Kishimura, A. Misaka and M. Sasago (Matsushita)

1:35pm A-2,”Super-Resolution Enhancement Method With Phase-Shifting Mask Available for Random Patterns”

A. Misaka and M. Sasago (Matsushita)

2:00pm A-3,”Low-Loss, High-Voltage 6H-SiC Epitaxial p-i-n Diode”

K. Fujihira, S. Tamura, T. Kimoto and H. Matsunami (Kyoto Univ.)

2:25pm A-4,”Sub-1um2 High Density Embedded SRAM Technologies for 100nm Generation SOC”

K. Tomita, K. Hasimoto, T. Inbe, T. Oasi, K. Tsukamoto, Y. Nishioka,

M. Matsuura, T. Eimori, M. Inuishi (Mitsubishi), I. Miyanaga, M. Nakamura,

T. Kishimoto, T. Yamada, K. Eriguchi, H. Yuasa, T. Satake, A. Kajiya

and M. Ogura (Matsushita)

Technical Session B Chaired by M. Niwa (Matsushita)

3:00pm B-1,”Impact of 0.10 um SOI CMOS with Body-Tied Hybrid Trench Isolation Structureto Break Through the Scaling Crisis of Silicon Technology”

Yuuichi Hirano, Takuji Matsumoto, Shigenobu Maeda, Toshiaki Iwamatsu, Tatsuya Kunikiyo, Kouji Nii, Kazuya Yamamoto, Yasuo Yamaguchi, Takashi Ipposhi, Shigeto Maegawa, and Masahide Inuishi (Mitsubishi)

3:25pm B-2,”Clarification of Floating-Body Effects on Drive Current and Short Channel Effect in Deep Sub-0.25um Partial Depleted SOI MOSFETs”

T. Matsumoto, S. Maeda, Y. Hirano, K. Eikyu, Y. Yamaguchi, S. Maegawa,

M. Inuishi and T. Nishimura (Mitsubishi)

3:50pm B-3,”Suppression of Leakage Current in SOI CMOS LSIs by Using Silicon-Sidewall Body-Contact (SSBC) Technology”

N. Kotani, S. Ito, T. Yasui, A. Wada, T. Yamaoka and T. Hori (Matsushita)

4:15pm B-4,”High Soft-Error Tolerance Body-Tied SOI Technology with Partial Trench

(PTI) for Next Generation Devices”

Y. Hirano, T. Iwamatsu, K. Shiga, K. Nii, K. Sonoda, T. Matsumoto,

S. Maeda, Y. Yamaguchi, T. Ipposhi, S. Maegawa and Y. Inoue (Mitsubishi)

4:40pm B-5,”A Novel Bi-layer Cobalt Silicide Process with Nitrogen Inplantation for

sub-50nm CMOS

K. Itonaga, K. Eriguchi, I. Miyanaga, A. Kajiya, M. Ogura, (Matsushita)

T. Tsutsumi, H. Sayama, H. Oda, T. Eimori and H. Morimoto (Mitsubishi)

5:05pm Closed Remark by D. Ueda (Matsushita)